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(R)
SP3203
3V RS-232 Serial Transceiver with Logic Selector
3 Driver/ 2 Receiver Architecture Logic selector function (VL) sets TTL input/output levels for mixed logic systems Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source Minimum 250Kbps data rate under load Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations ESD Specifications: +2kV Human Body Model Applications Palmtops Cell phone Data Cables PDA's
DESCRIPTION The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency, charge-pump that requires only 0.1F capacitors during 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance from a single power supply ranging from +3.0V to +5.5V. The SP3203 is a 3-driver/2-receiver device, with a unique VL pin to program the TTL input and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's and cell phones. Receiver outputs will not exceed VL for VOH and transmitter input logic levels are scaled by the magnitude of the VL input.
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC..................................................................-0.3V to +6.0V V+ (NOTE 1)..................................................-0.3V to +7.0V V- (NOTE 1)...................................................+0.3V to -7.0V V+ + |V -| (NOTE 1).........................................................+13V ICC (DC VCC or current)...........................................+100mA Input Voltages TxIN, SHUTDOWN = GND..........................-0.3V to +6.0V RxIN...............................................................................+25V
Output Voltages TxOUT.............................................................+13.2V RxOUT..............................................-0.3V to (VL + 0.3V) Short-Circuit Duration TxOUT................................................................Continuous Storage Temperature...............................-65C to +150C Power Dissipation per Packages 20-Pin TSSOP (derate 7.0mW/C above+70C)............................560mW
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
SPECIFICATIONS
(VCC = VL = +3V to +5.5V, C1-C4 = 0.1F, tested at +3.3V +10%, C1 = 0.047F, C2-C4 = 0.33F, tested at +5.0V +10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25C.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DC CHARACTERISTICS (VCC = +3.3V or +5V, TA = +25oC) Supply Current Shutdown Supply Current LOGIC INPUTS 0.8 Input Logic Threshold Low 0.6 2.4 2.0 Input Logic Threshold High 1.4 0.9 Transmitter Input Hystersis Input Leakage Current RECEIVER OUTPUTS Output Leakage Currents Output Voltage Low VL Output Voltage High 0.6 0.1 VL V IOUT = -1mA 0.05 10 0.4 A V RxOUT, receivers disabled IOUT = 1.6mA 0.5 0.01 1 V A TxIN, Shutdown V TxIN, Shutdown V TxIN, Shutdown VL = 2.5V VL = 5.0V VL = 3.3V VL = 2.5V VL = 1.8V VL = 3.3V or 5.0V 0.3 1 1 10 mA A Shutdown = VCC, no load Shutdown = GND
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
2
SPECIFICATIONS (continued)
(VCC = VL = +3V to +5.5V, C1-C4 = 0.1F, tested at +3.3V +10%, C1 = 0.047F, C2-C4 = 0.33F, tested at +5.0V +10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25C.)
PARAMETER RECEIVER INPUTS Input Voltage Range
MIN.
TYP.
MAX.
UNITS
CONDITIONS
-25 0.8 1.5
+25
V VL = 5.0V VL = 2.5V or 3.3V
Input Threshold Low 0.6 1.2 1.8 Input Threshold High 1.5 Input Hysteresis Input Resistance TRANSMITTER OUTPUTS Output Voltage Swing Output Resistance Output Short-Circuit Current Output Leakage Current 5 300 5.4 10M 60 25 3 0.5 5 7 2.4 2.4
V
TA = +25OC
V
TA = +25OC
VL = 5.0V VL = 2.5V or 3.3V
V k TA = +25OC
V mA A
All transmitter outputs loaded with 3k to TA = 25OC VCC = V+ = V- = 0, transmitter output = 2V VTxOUT = 0 VTxOUT = 12, transmitter disabled; VCC = 0 or 3.0V to 5.5V
PARAMETER Maximum Data Rate tPHL Receiver Propagation Delay tPLH Receiver Output Enable Time Receiver Output Disable Time Time to Exit Shutdown Transmitter Skew Receiver Skew
MIN. 250
TYP.
MAX.
UNITS kbps
CONDITIONS RL = 3k, CL = 1000pF, one transmitter switching Receiver input to receiver output CL = 150pF normal operation normal operation IVTxOUTI > 3.7V (Note 2)
0.15 s 0.15 200 200 100 100 50 ns ns s ns ns VCC = 3.3V TA = +25oC RL = 3k to 7k, measured from +3V to -3V or -3V to +3V
ItPHL -tPLHI ItPHL -tPLHI
6
30 V/s 30
CL = 150pF to 1000pF CL = 150pF to 2500pF
Transition-Region Slew Rate 4
Note 2. Transmitter skew is measured at the transmitter zero crosspoint.
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
3
NAME
FUNCTION
PIN NUMBER SP3203
C1+ V+ C1C2+ C2VR1IN R2IN R1OUT R2OUT T1IN T2IN T3IN T1OUT T2OUT T3OUT GND VCC SHUTDOWN VL
Positive terminal of the symmetrical charge-pump capacitor, C1. Regulated +5.5V output generated by the charge pump. Negative terminal of the symmetrical charge-pump capacitor, C1. Positive terminal of the symmetrical charge-pump capacitor, C2. Negative terminal of the symmetrical charge-pump capacitor, C2. Regulated -5.5V output generated by the charge pump. RS-232 receiver input. RS-232 receiver input. TTL/CMOS receiver output. TTL/CMOS receiver output. TTL/CMOS driver input. TTL/CMOS driver input. TTL/CMOS driver input. RS-232 driver output. RS-232 driver output. RS-232 driver output. Ground. +3.0V to +5.5V supply voltage. Apply logic LOW to shut down drivers and charge pump. Logic-Level Supply Voltage Selection
1 2 3 4 5 6 14 13 11 10 7 8 9 17 16 15 18 19 20 12
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
4
C1+ 1 V+ 2 C1- 3 + C2 4 C2- 5 VT1IN T2IN 6 7 8 SP3203
20
SHUTDOWN
19 VCC 18 GND 17 T1OUT 16 T2OUT 15 T3OUT 14 R1IN 13 R2IN 12 11 VL R1OUT
T3IN 9 R2OUT 10
Figure 7. SP3203 Pinout Configuration
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
5
+3V to +5.5V
C5
+
20 19 0.1F Shutdown VCC 1 C1+ 0.1F 3 4 C1C2+ C2T1IN T2IN
12 VL V+ C3 2 + 0.1F
C1
+
SP3203
C2
+
V-
6 C4 + 0.1F
0.1F
5 7
T1OUT T2OUT T3OUT R1IN 5K
17 RS-232 16 OUTPUTS
TTL/CMOS INPUTS
8
9 T3IN 11 R1OUT TTL/CMOS OUTPUTS 10 R2OUT
15 14 RS-232 INPUTS
R2IN 13 5K
GND 18
Figure 8. SP3203 Typical Operating Circuit
Rev. 6/25/03 SP3203 (c) Copyright 2003 Sipex Corporation
6
DESCRIPTION The SP3203 is a 3-driver/2-receiver device that can be operated as a full duplex, RS-232 serial transceiver with the 3rd driver acting as a control line allowing a Ring Indicator (RI) signal to alert the UART on the PC. This transceiver meet the EIA/TIA-232 and ITUT V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers, PDA's and cell phones. The SP3203 devices feature Sipex's proprietary and patented (U.S.#5,306,954) on-board charge pump circuitry that generates 5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3203 devices can operate at a minimum data range of 250kbps, driving a single driver. The SP3203 is a 3-driver/2-receiver device. THEORY OF OPERATION The SP3203 contains four basic circuit blocks: 1. drivers, 2. receivers, 3. a Sipex proprietary charge pump and 4. VL circuitry. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. The driver output stages are turned off (High Impedance) when the device is in shutdown mode. The drivers typically can operate at a data rate of 250Kbps. The drivers can guarantee a data rate of 120Kbps fully loaded with 3K in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.
The slew rate of the driver output is internally limited to a maximum of 30V/s in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. The SP3203 driver can maintain high data rates up to 250Kbps with a single driver loaded. Figure 9 shows a loopback test circuit used to test the RS-232 Drivers. Figure 10 shows the test results of the loopback circuit with all three drivers active at 120Kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 11 shows the test results where one driver was active at 250Kbps and all three drivers loaded with an RS-232 receiver in parallel with a 1000pF capacitor. The transmitter inputs do not have pull-up resistors. Connect unused inputs to ground or VL Receivers The receivers convert 5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers are disabled when in shutdown. The truth table logic of the SP3203 driver and receiver outputs can be found in Table 1. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is immune to noisy transmission lines. Should an input be left unconnected, an internal 5K pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump is a Sipex-patented design (U.S. #5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses a four-phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
7
DEVICE: SP3203 SHUTDOWN 0 1 TXOUT High-Z Active RXOUT High-Z Active Charge Pump Inactive Active
C5 + 0.1F 1 C1+ 0.1F 3 C14 C2+ C2 + 0.1F 5 C2T1IN TTL/CMOS INPUTS TXIN
+3V to +5V
19 VCC V+ 2 C3 + 0.1F
C1
+
SP3203
V-
6 C4 + 0.1F
Table 1. SHUTDOWN Truth Table.
(Note: When device in shutdown, the SP3203's charge pump is turned off and V+ decays to VCC. V- is pulled to ground and the transmitter outputs are disabled as High Impendance).
T1OUT
TXOUT
R1OUT TTL/CMOS OUTPUTS 5K RXOUT 5K VCC 20 SHUTDOWN
R1IN
consists of a regulated dual charge pump that provides output voltages of 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a of 5.5V, the charge pump is enabled. If the output voltages exceed a of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 12). A description of each phase follows. VSS Charge Storage-Phase 1(Figure 13) During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC.
RXIN
1000pF 1000pF
12 VL GND 18
+3V to +5.5V
Figure 9. Loopback Test Circuit for RS-232 Driver Data Transmission Rates
VSS Transfer-Phase 2 (Figure 14) Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. VDD Charge Storage-Phase 3 (Figure 15) The third phase of the clock is identical to the first phase -- the charge transferred in C1 pro-
[
T
]
[ T ]
T1 IN 1
T
T1 IN 1 T
T1 OUT 2 T T
T T1 OUT 2 T
R1 OUT 3
R1 OUT 3
Ch1 5.00V Ch2 5.00V M 5.00s Ch1 Ch3 5.00V
0V
Ch1 5.00V Ch2 5.00V M 2.50s Ch1 Ch3 5.00V
0V
Figure 10. Loopback Test Circuit Result at 120Kbps (All Drivers Fully Loaded)
Rev. 6/25/03
Figure 11. Loopback Test Circuit result at 250Kbps (All Drivers Fully Loaded)
SP3203 (c) Copyright 2003 Sipex Corporation
8
duces -VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. VDD Transfer-Phase 4 (Figure 16) The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC, in a no-load condition, V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent ineffiencies in the design. The clock rate for the charge pump is typically operates at 250kHz. The external capacitors are usually 0.1F with a 16V breakdown voltage rating. VL Supply Level Current RS-232 serial tranceivers are designed with fixed 5V or 3.3V TTL input/output voltages levels. The VL function in the SP3203 allows the end user to set the TTL input/output voltage levels independent of VCC. By connecting VL to the main logic bus of system, the TTL input/ output limits and threshold are reset to interface with the on board low voltage logic circuity.
Capacitor Selection Table: VCC (V) 3.0 to 3.6 4.5 to 5.5 3.0 to 5.5 C1 (F) 0.1 0.047 0.22 C2-C4(F) 0.1 0.33 1
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
9
[
T
] +6V
a) C2+
1 2 2
T
0V 0V
b) C2T -6V Ch1 2.00V Ch2 2.00V M 1.00s Ch1 1.96V
Figure 12. Charge Pump Waveforms
Figure 13. Charge Pump -- Phase 4 - VSS Charge Storage
Figure 14. Charge Pump -- Phase 3 - VSS Charge Transfer
Figure 15. Charge Pump -- Phase 2 - VDD Charge Storage
Figure 16. Charge Pump -- Phase 1 - VDD Charge Transfer
Rev. 6/25/03 SP3203 (c) Copyright 2003 Sipex Corporation
10
C5
+
0.1F
C1
+
19 20 Shutdown VCC 1 C1+ 3 C14 C2+
12 VL V+ 2 C3 + 0.1F
0.1F
SP3203
C2
+
V- 6 C4 + 0.1F
0.1F
5 C27 T1IN 8 T2IN 9 T3IN
T1OUT
17
T2OUT 16 T3OUT 15
11 R1OUT 10 R2OUT
R1IN 14 R2IN 13
DB-9 Connector 6 7 8 9
6. 7. 8. 9. DCE Ready Request to Send Clear to Send Ring Indicator
GND 18
1 2 3 4 5
DB-9 Connector Pins: 1. Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground (Common)
Figure 17. Circuit for the connectivity of the SP3203 with a DB-9 connector
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
11
ESD TOLERANCE The SP3203 incorporates ruggedized ESD cells on all driver output and receiver input pins. The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body's potential to store electro-static energy and
RC C SW1
DC Power Source
discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 18. This method will test the IC's capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS ) are 15k and 100pF, respectively.
RS S SW2 SW2 CS S
Device Under Test
Figure 18. ESD Test Circuit for Human Body Model
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
12
PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP)
e
0.126 BSC (3.2 BSC) 0.252 BSC (6.4 BSC) 1.0 OIA 0.169 (4.30) 0.177 (4.50)
DIMENSIONS in inches (mm) Minimum/Maximum Symbol D e 20 Lead 0.252/0.260 (6.40/6.60) 0.026 BSC (0.65 BSC)
0.039 (1.0)
0'-8' 12'REF e/2 0.039 (1.0) 0.043 (1.10) Max D 0.033 (0.85) 0.037 (0.95)
0.007 (0.19) 0.012 (0.30)
0.002 (0.05) 0.006 (0.15) (2) 0.008 (0.20)
0.004 (0.09) Min
0.004 (0.09) Min Gage Plane
0.010 (0.25)
(3) 1.0 REF
0.020 (0.50) 0.026 (0.75)
(1)
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
13
ORDERING INFORMATION

Model SP3203CY SP3203EY
Temperature Range 0C to +70C -40C to +85C
Package Types 20-pin TSSOP 20-pin TSSOP
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
ANALOG EXCELLENCE
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Rev. 6/25/03
SP3203
(c) Copyright 2003 Sipex Corporation
14

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